NCT7491
http://onsemi.com
37
GPIO1
" Bit 7 of register 0x80 sets GPIO1 direction. 1=Input,
0=Output
" Bit 5 of register 0x80 sets GPIO1 polarity. 1=active
high, 0=active low
" Bit 3 of register 0x80 is GPIO1 data. If GPIO1 is an
input this bit shows the pin state. If it is an output then
this bit sets the output state.
GPIO2
" Bit 6 of register 0x80 sets GPIO2 direction. 1=Input,
0=Output
" Bit 4 of register 0x80 sets GPIO2 polarity. 1=active
high, 0=active low
" Bit 2 of register 0x80 is GPIO2 data. If GPIO2 is an
input this bit shows the pin state. If it is an output then
this bit sets the output state.
GPIO3
" Bit 7 of register 0x85 sets GPIO3 direction. 1=Input,
0=Output
" Bit 6 of register 0x85 sets GPIO3 polarity. 1=active
high, 0=active low
" Bit 5 of register 0x85 is GPIO3 data. If GPIO3 is an
input this bit shows the pin state. If it is an output then
this bit sets the output state.
When writing to a GPIO pin that is configured as an output
the polarity must be taken into account. For example, if the
pin is set as active low then writing a 1 to the data bit will pull
the GPIO pin low.
When GPIOs are configured as inputs the data bit always
shows the actual pin state.
VCCP Low Detection
If the processor core voltage is being monitored on the
Vccp channel and the NCT7491 is run from the auxiliary
rail, then the user can enable a function to suspend various
functions in the NCT7491 when the core voltage falls below
a programmable threshold.
Setting bit 6 of register 0x10 enables the Vccp Low
function. In this mode, if the Vccp voltage falls below the
value in the Vccp Low Limit register (0x46) then the Vccp
status bit is set, the THERM timer function is disabled, PECI
errors are cleared, SMBus Master errors are cleared and all
PWM outputs shut down. When the Vccp voltage increases
above the Vccp Low Limit then any of the above functions
that were previously enabled will become active again.
XNOR Tree Test Mode
The NCT7491 includes an XNOR tree test mode. This
mode is useful for incircuit test equipment at boardlevel
testing. By applying stimulus to the pins included in the
XNOR tree, it is possible to detect opens, or shorts, on the
system board.
The XNOR tree test is invoked by setting Bit 0 (XEN) of
the XNOR Tree Test Enable register (Register 0x6F).
Figure 25 shows the signals that are exercised in the XNOR
tree test mode.
PWM1/XTO
PWM3
PWM2
TACH4
Figure 25. XNOR Tree Test
TACH3
TACH2
TACH1
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